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我们研制了具有2500个高速低功耗CML门电路(每个门的延迟1毫微秒,功耗5毫瓦)的梁式引线多片结构高速双极性LSI器件。这些LSI用于大型数据处理系统必须同时满足低成本、高性能和高可靠性等三方面的要求。对于这些要求,我们通过用水平不高的电路技术、LSI结构和适中的工艺水平等新的设计考虑。成功地实现了。这样,使我们确信用这些LSI装备大型数据处理系统,将给我们带来良好的价格性能比。
We developed a high-speed, multi-chip, high-speed, bipolar LSI device with 2,500 high-speed, low-power CML gate circuits with 1 nanosecond delay per gate and 5 milliwatts of power consumption. These LSIs are intended for large data processing systems that must meet the requirements of both low cost, high performance and high reliability. For these requirements, we adopted new design considerations such as low-level circuit technology, LSI architecture, and moderate process levels. Successfully achieved. In this way, we are convinced that the LSI equipped with these large data processing systems, will give us a good price performance ratio.