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一、MC6800(MPU)信号描述MC6800单片构成如图4—1示。总线电平:标准TTL电平;统一编址,因而总线控制简单;主频为1MC,二相时钟。其信号描述如下。1.φ_1φ_2—二相非重叠的时钟。时钟的频率为1Mc,仅输入到处理器不是标准的TTL电平。2.地址总线A_0～A_(15)共16根,其输出是三态总线驱动器,能驱动一个标准的TTL负载和130PF电容负载。3.数据总线D_0～D_7共8根,双向的,写入时必须由数据总线允许DBE控制。4.HALT停机:机器停在一条指令的末尾,总线有效信号为“1”电平,有效地址是“0”电平,所有的其它三态线将在三态方式中。停机信号HALT不能在φ_1的后250ns时间中产生,以保证单指令操作,因
A, MC6800 (MPU) Signal Description MC6800 monolithic structure shown in Figure 4-1. Bus level: standard TTL level; unified addressing, so the bus control is simple; clocked at 1MC, two-phase clock. The signal is described below. 1.φ_1φ_2-two-phase non-overlapping clock. The clock frequency is 1Mc, only the input to the processor is not a standard TTL level. 2. Address bus A_0 ~ A_ (15) a total of 16, the output is a three-state bus driver that can drive a standard TTL load and 130PF capacitive load. 3. Data bus D_0 ~ D_7 a total of eight, two-way, the data must be written to allow DBE bus control. 4.HALT stop: the machine stops at the end of an instruction, the bus valid signal is “1” level, the valid address is “0” level and all other tri-state lines will be in tri-state mode. The shutdown signal HALT can not be generated in the last 250ns of φ_1 to ensure single instruction operation because