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上期要求我们设计的电路是当输入信号U_H在0～14V范围变化时,其输出U_X应为如图1所示的被箝位于28V-22V=6V不变;当U_H小于4V使U_(X1)>7.5V时,稳压管D2被击穿,有电流自运放A输出端经R、D2流入电源地,此时U_X被D2箝位于7.5V不再随U_H及U_(X1)变化,实现了前述设计要求。上期讲座中也已经讨论过这种稳压管箝位方案作为设计思路是正确的,实际并不可行。可行的方案是用集成运放实现了“有源稳压管”代替D1的设计如上期图4。借鉴同样的设计思路我们也能设计出代替D2的“有源稳压管”,完整的有源箱位电路如图3所示。运放B、二极管D1等代替了图2中的7.5V稳压管,通过电位器R_(W1)可调出准确的
The circuit we designed in the previous issue is when the input signal U_H is in the range of 0 ~ 14V, the output U_X should be clamped at 28V-22V = 6V as shown in Figure 1. When U_H is less than 4V, U_ (X1) > 7.5V, the voltage regulator diode D2 is breakdown, and current flows from the A output terminal of the operational amplifier to the power ground via R and D2. At this time, U_X is clamped at 7.5V by D2 clamp and no longer changes with U_H and U_ (X1) The above design requirements. This talk about the voltage regulator clamp has also been discussed as a design idea is correct, the actual is not feasible. A viable solution is to use an integrated op amp to achieve the “active regulator” instead of the design of D1 as shown in Figure 4 above. From the same design ideas we can also design an alternative to the D2 “active regulator”, a complete active tank circuit shown in Figure 3. Op amp B, diode D1 instead of 7.5V regulator in Figure 2, through the potentiometer R_ (W1) can be adjusted out of accurate