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本文对采用晶体管和隧道二极管相组合的基本组件作了描述。对用这种组件构成的比较器和半加器进行了定性讨论。介绍了全加器电路的详细设计和容差分析,并推导出满足容差要求的最佳设计公式。对全加器电路的进位部分进行了开关分析。结果表明,在一般接线情况下杂散元件(而不是真实的器件)的性能是造成进位延迟的主要因素。文章介绍了一个八位加法器的试验结果。加法器每一级的平均进位延迟时间为3/4毫微秒。
This article describes the basic components of a combination of transistors and tunnel diodes. A qualitative discussion of comparators and half-adders made of such components is made. Described the full adder circuit design and tolerance analysis, and to derive the tolerance to meet the requirements of the best design formula. Carry on the switch analysis to carry part of full adder circuit. The results show that the performance of stray components (rather than real devices) in the case of normal wiring is the main factor causing the carry delay. The article describes the test results of an eight-bit adder. The average carry delay for each stage of the adder is 3/4 nanoseconds.