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数字电路逻辑综合是90年代为大规模ASIC自动化设计发展起来的一种全新电子设计自动化（EDA）工具。本文将详细介绍逻辑综合工具的结构特点和设计方法．
Digital Circuit Logic Synthesis is a new electronic design automation (EDA) tool developed in the 1990s for large-scale ASIC automation design. This article will detail the structural features and design methods of the logic synthesis tool.