Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor fi

• 作 者: 马达 罗小蓉 魏杰 谭桥 周坤 吴俊峰
• 机 构: State Key Laboratory of Electronic Thin Films and Integrated Devices.University of Electronic Scienc
• 出 处: Chinese Physics B
• 发表日期: 2016年04期
• 关键词: VDMOS pillar transistor trench drain oxide breakdown capacitance doping junction

A new ultra-low specific on-resistance(Ron,sp) vertical double diffusion metal–oxide–semiconductor field-effect transistor(VDMOS) with continuous electron accumulation(CEA) layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration(Nn). In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp.Especially, the two PN junctions within the trench gate support a high gate–drain voltage in the off-state and on-state, respectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS(CSJ-VDMOS)at the same high breakdown voltage(BV).

A new ultra-low specific on-resistance (Ron, sp) vertical double diffusion metal-oxide-semiconductor field-effect transistor (VDMOS) with continuous electron accumulation It has a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from The source to the drain in a cell pitch. This mechanism does not significantly short reduces the Ron, sp but also makes the Ron, sp almost independent of the n-pillar doping concentration (Nn). In off-state, the depletion between the n -pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron, sp .Especially, the two PN junctions within the trench gate support a high gate-drain voltage in the off-state and on- state, respectively. However, the Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron, sp by 80% compared with the conventional super-junction VDMOS (CSJ-VDMOS) at the same high breakdown voltage (BV).