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在逻辑设计中经常用到的CMOS双时钟式可逆计数器,虽然有便于进行加法、减法交替计数的优点,但是它对两个时钟脉冲之间的关系有一定的要求.器件功能真值表规定:两个时钟输入端互为对方的“允许”端,即其中一端为高电平时,另一端的输入才起作用.相反,当一个输入端的时钟上升沿对应另一端为低电平时,这个计数脉冲将是“无效”的.因此,加脉冲和减脉冲之间必须留有间隔.这一点在许多有时钟发生器的控制系统
Although the CMOS dual-clocked reversible counter, which is often used in logic design, has the advantage of being able to count alternately by addition and subtraction, it has certain requirements on the relationship between two clock pulses. The device’s functional truth table states: The two clock inputs are “allowed” for each other, that is, the input on the other side is effective when one of the two clock inputs is high, whereas on the other hand, the rising edge of the clock on one input is low, The count pulse will be “invalid.” Therefore, there must be a gap between plus and minus pulses This is true in many control systems with a clock generator