一种速度低于100ns的256kDRAM

• 作 者: Tomio Narano 李儒章
• 出 处: 微电子学
• 发表日期: 1985年Z1期
• 关键词: 时钟发生器 存取时间 随机存取 管芯 芯片尺寸 电路技术 读出放大器 噪声抗扰度 单元阵列 半字节

动态随机存取存贮器(DRAM)不仅在密度方面一直在提高,而且在实现高速度方面也在提高。由于三层多晶硅技术和增压高电平时钟发生器电路的使用,一种管芯面积为34.1mm~2、速度低于100ns的DRAM已经获得。这种器件能够以一个CAS时钟的15ns存取时间的半节型工作,并且也能够用CAS先于RAS的时序刷新。

Dynamic random access memory (DRAM) not only has been increasing in density, but also in terms of achieving high speed. Due to the triple-layer polysilicon technology and the use of a boost high-level clock generator circuit, a DRAM with a die area of ​​34.1 mm2 and a speed of less than 100 ns has been obtained. The device is capable of operating as a half-node with a 15 ns access time to a CAS clock and can also be refreshed with CAS prior to RAS timing.