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Non-binary low density parity check (NB-LDPC) codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios (SNR) are required.They have better burst error correcting performance,especially with high order Galois fields (GF).A shared comparator (SCOMP) architecture for elementary of check node (ECN)/elementary of variable node (EVN) to reduce decoder complexity is introduced because high complexity of check node (CN) and variable node (VN) prevent NB-LDPC decoder from widely applications.The decoder over GF(16) is based on the extended min-sum (EMS) algorithm.The decoder matrix is an irregular structure as it can provide better performance than regular ones.In order to provide higher throughput and increase the parallel processing efficiency,the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules.The decoder complexity can be reduced by 28％ from traditional decoder when SCOMP architecture is introduced.The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations.The proposed architecture can be conveniently extended to GF such as GF(64) or GF(256).Compared with previous works,the decoder proposed in this paper has better hardware efficiency for practical applications.