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本文应用按比例缩小原理缩小单个电路2114RAM的芯片尺寸,成功地试制出4微米多晶硅栅的RAM,并获得良好的工作性能,已从试制转入大批量生产。按比例缩小后,显著地提高了成品率,并与5微米多晶硅栅的RAM作了比较. MOS管的增益与W/L成正比,按比例缩小(?),W应当以同样的比例缩小.不仅缩小MOS管、多晶电阻、电容等元件本身的形状,而且对掩模套准误差和隔离宽度等也要相应缩小;即使只考虑元件部分,也不仅仅是简单地缩小面积,诸如氧化膜厚度、结深等也要减小. 制作工艺是采用标准硅栅等平面技术;对RAM的外围电路采用耗尽型/增强型制作在高阻P型硅衬底上.存贮矩阵中是由增强型MOS(?)和两个离子注入多晶硅负载电阻组
In this paper, the principle of scaling down the size of a single circuit 2114RAM chip size, the successful trial of a 4 micron polysilicon gate RAM, and get good performance, from the trial into mass production. After scaling down, the yield is significantly improved and compared to the RAM of the 5 micron polysilicon gate. The gain of the MOS transistor is proportional to W / L, scaled down (?), And W should be reduced by the same ratio. Not only to reduce the shape of the MOS transistor, polycrystalline resistance, capacitors and other components itself, but also to mask the registration error and isolation width, etc. should be reduced accordingly; even consider only part of the component, not only simply reduce the area, such as oxide film Thickness, junction depth should also be reduced. The production process is the use of standard silicon gate and other planar technology; the use of depletion / enhancement of the peripheral circuits of RAM in the high-resistance P-type silicon substrate storage matrix Enhanced MOS (?) And two ion implanted polysilicon load resistors