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在单个硅片上布置几百个逻辑门的能力,对减少功率,提高速度和降低成本有很大潜力。可是,要发挥大规模集成电路(LSI)的这些优点,尚有若干问题须待解决。这篇论文讨论的逻辑设计方法,能大大简化LSI 的测试、诊断和现场服务。该设计方法基于两个概念,这两个概念彼此几乎不相关,但又有效地结合在一起。第一,设计的时序逻辑结构要求正确操作与信号上升、下降时间,或与电路或导线上的延迟时间无关。第二,所有内部存贮元件的设计(而不是存贮阵列),要求它们还可作为移位寄存器工作,从而简化了测试和诊断。测试困难的时序逻辑则可转换为组合逻辑,所以测试便易于进行。这种转换是在测试期间完成的。这种设计的优点和对成本的影响本文也将定性的讨论。
The ability to place hundreds of logic gates on a single silicon has great potential for reducing power, increasing speed, and reducing costs. However, there are still some problems to be solved in order to take full advantage of these advantages of large-scale integrated circuits (LSIs). The logical design methodology discussed in this paper can greatly simplify LSI's testing, diagnostics, and field service. The design approach is based on two concepts that are almost irrelevant to each other but effectively combined. First, the design of the timing logic structure requires correct operation and signal rise, fall time, or with the circuit or wire delay time has nothing to do. Second, the design of all internal storage elements (rather than storage arrays) requires that they also work as shift registers, simplifying testing and diagnostics. Tested timing logic can be converted to combinational logic, so testing is easy. This conversion is done during the test. The advantages of this design and the impact on costs will also be qualitatively discussed in this article.