Research on Latch-up Issue in the Chip-level ESD Power-up Test

• 作 者: XuChenghang;WuJianfei;LiJiancheng;PengRuijie;GuoYin;
• 机 构: National University of Defence Technology, Changsha 410073, China
• 出 处: 第十七届计算机工程与工艺年会暨第三届微处理器技术论坛
• 发表日期: 2013年期

　　An IC-level electrostatic discharge (ESD) test method to test the power-up chip is introduced in this paper.The power-up ESD (PESD) test results can be classified into 3 grades: pass, latch-up and damage.In practical applications, the results of PESD are often worse than power-down ESD test.Latch-up is a peculiarly phenomenon in power-up test.During the test, the huge current in latch-up issue may lead to damage of the IC.The damage caused by latch-up issue is studied and the impact of power supply voltage on the latch-up issue is analyzed in this paper.