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通过解一维泊松方程,对均匀掺杂的P型硅衬底MOS电容器进行了数值模拟,研究了衬底厚度和背接触势垒对衬底内的电势分布和载流子密度分布的影响.模拟计算结果表明,在硅衬底厚度超过两倍最大耗尽层厚度时,背接触与正界面之间存在一个电中性区,背接触不会影响MOS电容器的性能;在硅衬底的实际厚度比两倍最大耗尽层厚度要小的情况下,背接触势垒对MOS电容器性能有明显的影响:当背接触势垒高度为零伏或负值时,MOS电容器的强反型阈电压随着硅衬底厚度的减薄而增加;当背接触势垒高度为正值时,随着硅衬底厚度的减薄,会出现阈电压先减小后增加的现象.
By solving the one-dimensional Poisson equation, the uniformly doped P-type silicon substrate MOS capacitor is numerically simulated. The effects of substrate thickness and back contact barrier on the potential distribution and carrier density distribution in the substrate are studied The simulation results show that there is an electrically neutral region between the back contact and the positive interface when the thickness of the silicon substrate exceeds twice the maximum depletion layer thickness and the back contact does not affect the performance of the MOS capacitor. When the actual thickness is smaller than twice the maximum depletion layer thickness, the back contact barrier has a significant effect on the performance of the MOS capacitor: when the back contact barrier height is zero volt or negative, the MOS capacitor’s strong inversion threshold The voltage increases with the decrease of the thickness of the silicon substrate. When the height of the back contact barrier is positive, as the thickness of the silicon substrate decreases, the threshold voltage first decreases and then increases.