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Single-Pole Double-Throw (SPDT) broadband switch has been designed in a 0.25μm Comple- mentary Metal Oxide Semiconductor (CMOS) process. To optimize the performance of isolation and insertion loss, based on normal design, the effects of Gate Series Resistances (GSR) on insertion loss and switching time are analyzed for the first time. The compatible GSRs are chosen by the analyses. The fabricated chips were tested and the results show the switch isolation from DC (Direct Current) to 1GHz exhibits 55dB and insertion loss lower than 2.1dB.
Single-Pole Double-Throw (SPDT) broadband switch has been designed in a 0.25 μm Complementary Metal Oxide Semiconductor (CMOS) process. To optimize the performance of isolation and insertion loss, based on normal design, the effects of Gate Series Resistances The fabricated chips were tested and the results show the switch isolation from DC (Direct Current) to 1 GHz exhibits 55 dB and insertion loss (GSR) on insertion loss and switching time are analyzed for the first time. The compatible GSRs are chosen by the analyzes lower than 2.1dB.