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通过对传统的全数字多相位时钟产生电路进行分析和总结,提出一种新颖的延时校准算法。该算法通过优化调整延时单元的顺序,大大改善了全数字多相位时钟产生电路的非线性。整个电路基于全数字延迟锁相环,采用0.13μm CMOS工艺实现,并成功用于时间数字转换器中。输入时钟频率范围在110 MHz到140 MH间,对应的输出相位差为446 ps到568 ps,积分非线性小于0.35 LSB,微分非线性小于0.33 LSB。
By analyzing and summarizing the traditional all-digital multi-phase clock generation circuit, a novel delay calibration algorithm is proposed. The algorithm greatly improves the non-linearity of all-digital multi-phase clock generation circuit by optimizing the sequence of delay cells. The entire circuit is based on an all-digital delay-locked loop implemented in a 0.13μm CMOS process and used successfully in time-to-digital converters. The input clock frequency ranges from 110 MHz to 140 MHz, with a corresponding output phase difference of 446 ps to 568 ps, an integrated nonlinearity of less than 0.35 LSB, and a differential nonlinearity of less than 0.33 LSB.