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结合新一代高集成度三维集成电路和新型相变存储技术,以三维相变存储单元阵列的实现为目标,进行了用于存储单元的驱动和开关作用的二极管阵列的制备实验。在借助低温等离子体活化键合技术获得了良好的键合界面之后,利用智能剥离法成功转移了单晶PN结二极管层到含有金属W电极阵列的基片上,并制备了垂直二极管阵列。经过聚焦离子束加工和电镜观察得知基片上小型W电极与转移来的PN结构Si层接触良好,测试得到了标准的二极管特性曲线,开关比达到4个数量级。不过实验制备的二极管漏电流较大,开关比偏低,这些问题还需要在将来实验环境的改进和工艺的优化中得到解决。
Combining with a new generation of highly integrated three-dimensional integrated circuits and a novel phase-change memory technology, the preparation of a diode array for the driving and switching of memory cells is performed with the goal of realizing a three-dimensional phase change memory cell array. After a good bonding interface was obtained by low-temperature plasma activated bonding, a single PN junction diode layer was successfully transferred onto a substrate containing a metal W electrode array by smart lift-off and a vertical diode array was prepared. After focused ion beam processing and electron microscope observation, the small W electrode on the substrate is in good contact with the Si layer of the transferred PN structure, and the standard diode characteristic curve is obtained by testing, and the switching ratio reaches 4 orders of magnitude. However, the experimentally prepared diodes have larger leakage current and lower switching ratio, and these problems still need to be solved in the future improvement of the experimental environment and process optimization.