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设计工程师有能力、也希望对评估的微处理器进行分类,并最终选出适于特定任务的最佳解决方案,通常是从性能和成本两个方面去考虑。在过去,微处理器结构的分类很容易:要么是冯诺曼结构,要么是哈佛结构。但是,CISC和RISC微处理器(MPU)/微控制器(MCU)和DSP芯片的大发展使各种器件的比较和分类非常困难。然而还有一些方法可以完成此项任务。 评估处理器性能的常用尺度是指令字的位数。但这种方法很快就遇到问题。我们是指操作码的长度?还是指整条指令的长度?在后一种情形中,涉及的要素包括源地址/目标地址/寄存器、以及为了形成数据的实际地址必须加到寄存器上的任何立即数据或位移量。如果是指后者,我们是用最小情况还是最大情况来作为指令长度?对于哈佛型结构,这种方法可能会把一个4位的MCU分类为10位、12位、甚或14位器
Design engineers have the ability and also want to classify the evaluation of the microprocessor, and ultimately choose the best solution for a particular task, usually from the performance and cost considerations. In the past, the classification of microprocessor architectures was easy: either the von Norman structure or the Harvard structure. However, the advent of CISC and RISC microprocessors (MPU) / microcontrollers (MCUs) and DSP chips has made the comparison and classification of various devices very difficult. However, there are ways to accomplish this task. A common metric for evaluating processor performance is the number of bits in the instruction word. But this method soon encountered problems. Do we mean the length of the opcode or the length of the entire instruction? In the latter case, the elements involved are the source address / destination address / register, and any immediate, which must be added to the register in order to form the actual address of the data Data or displacement. If it refers to the latter, do we use the minimum or maximum size as the instruction length? For a Harvard-type architecture, this method might sort a 4-bit MCU into 10, 12, or even 14 bits