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加法器的设计往往是将多个全加器级联起来实现 ,在耗费资源和速度上没有进行优化。借助 EDA逻辑综合工具实现的加法器克服了上述缺点 ,且简单方便
Adder design often cascade multiple full adders to achieve, with no cost and speed optimization. The adder implemented with the EDA logic synthesis tool overcomes these shortcomings and is simple and convenient