两微米外延N阱CMOS艺的研究

• 作 者: 马槐楠 徐葭生
• 机 构: 清华大学微电子学研究所,清华大学微电子学研究所
• 出 处: 半导体学报
• 发表日期: 1987年04期
• 关键词: 外延层 反相器 短沟效应 电路部分 NMOS 沟道长度 瞬态 PMOS 噪声容限 栅氧化层

本文描述2μm外延N阱CMOS工艺的研究,在工艺模拟和实验的基础上制定了合理的、可行的工艺流程.在工艺中成功地应用了全离子注入和红外瞬态退火技术.实验结果表明,2μm CMOS 器件具有优良的特性,适合超大规模集成电路的要求.5伏工作电压,21级2μmCMOS反相器环振链的级延时是0.48ns,每级的延时功耗乘积是0.49pJ.P~-/P~+外延层结合N阱伪集电极保护环,可在CMOS电路中最易产生Latch-up的I/O电路部分保证不发生Latch-up.本工艺可以应用于超大规模集成电路的制作.

This paper describes the research of 2μm epitaxial N-well CMOS process, and based on the process simulation and experiment, a reasonable and feasible process flow is established.The all-ion implantation and the infrared transient annealing technology are successfully applied in the process.The experimental results show that, 2μm CMOS devices have excellent characteristics, suitable for VLSI requirements .5-volt operating voltage, 21-level 2μmCMOS inverter ring oscillator stage delay is 0.48ns, delay power consumption per product is 0.49pJ. P ~ - / P ~ + epitaxial layer combined with N-well pseudo-collector protection ring, the Latch-up is most likely to be generated in the CMOS circuit Latch-up part of the I / O circuit to ensure that this process can be applied to VLSI Circuit production.