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本文叙述一个每秒44兆位串行流水线乘法器,它采用新颖的线路结构实现高效算法。此乘法器用于带符号的数值系数(SM)与任意字长的2的补码数(TC)相乘,产生的乘积自动舍入并截取与输入数相同的字长。电路设计集中研究位单元——一个与系数字的一位相对应的电路单元。由这样的位单元,可以构成任意复杂的乘法器。实际实现的乘法器包含4个位
This article describes a 44 megabit per second serial pipeline multiplier that uses a novel circuit architecture for efficient algorithms. This multiplier is used to multiply the signed value coefficient (SM) by two’s complement (TC) of any word length and the resulting product is automatically rounded and truncated to the same word size as the number of inputs. Circuit design focuses on bit cells - one that corresponds to one bit of the coefficient word. By such a bit unit, an arbitrary complicated multiplier can be constructed. The actual implementation of the multiplier contains 4 bits