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通过对高压管的优化设计,门阵列外围pad的优化设计及门阵列内部的逻辑设计,进行了高低压兼容门阵列的研究。高压管的优化设计是通过实验方法,对具有源场极漂移区的NMOS高压管进行优化,从而得到其源场极长度、漂移区长度、沟道长度、漂移区浓度及深度的优化值。pad的设计是采用传输延时最小理论确定各缓冲器尺寸,版图上采用人工最佳布局布线。内部逻辑的设计是利用Apollo工作站的chipsmith软件进行逻辑模拟及自动布局布线完成。
Through the optimal design of high-pressure pipe, the optimal design of the pad of the gate array and the logic design of the gate array, the research on the high and low voltage compatible gate array is carried out. The optimal design of high-pressure pipe is to optimize the NMOS high-pressure pipe with source field drift region by experimental method, so as to obtain the optimized values of source field length, drift region length, channel length, drift region concentration and depth. The design of the pad is to use the transmission delay minimum theory to determine the buffer size, the layout of the best use of artificial layout. Internal logic design is to use Apollo workstation chipsmith software for logic simulation and automatic placement and routing completed.