【摘 要】
：
We fabricated a set of symmetric gate-recess devices with gate length of 70 nm.We kept the source-to-drain spacing(LsD) unchanged,and obtained a group of devices with gate-recess length (Lrecess) from 0.4 μm to 0.8 μm through process improvement.In order
【机 构】
：
High-Frequency High-Voltage Device and Integrated Circuits Center,Institute of Microelectronics,Chin
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We fabricated a set of symmetric gate-recess devices with gate length of 70 nm.We kept the source-to-drain spacing(LsD) unchanged,and obtained a group of devices with gate-recess length (Lrecess) from 0.4 μm to 0.8 μm through process improvement.In order to suppress the influence of the kink effect,we have done SiNx passivation treatment.The maximum saturation current density (ID_max) and maximum transconductance (gm,max) increase as Lrecess decreases to 0.4 μm.At this time,the device shows ID_max =749.6 mA/mm at VGS =0.2 V,VDS =1.5 V,and gm_max =1111 mS/mm at VGS =-0.35 V,VDS =1.5 V.Meanwhile,as Lrecess increases,it causes parasitic capacitance Cgd and gd to decrease,making fmax drastically increases.When Lrecess =0.8 μm,the device shows fT =188 GHz and fmax =1112 GHz.
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