Impact of Band-Engineering to Performance of High-k Multilayer Based Charge Trapping Memory

• 作 者: 刘利芳 潘立阳 张志刚 许军
• 机 构: Institute of Microelectronics,Tsinghua University,Graduate School at Shenzhen,Tsinghua University,
• 出 处: Chinese Physics Letters
• 发表日期: 2015年08期
• 关键词: erase trapping tunneling trapped serving modulated closer blocking satisfy reten

Impact of band-engineering to the performance of charge trapping memory with HfO_2/Ta_2O_5/HfO_2(HTH) as tie charge trapping layer is investigated.Compared with devices with the same total HfO_2 thickness,structures with Ta_2O_5 closer to substrates show larger program/erase window,because the 2nd HfO_2(next to blocking oxide)serving as part of blocking oxide reduces the current tunneling out of/in the charge trapping layer during program and erase.Moreover,trapped charge centroid is modulated and contributed more to the flat-band voltage shift.Further experiments prove that devices with a thicker 2nd HfO_2 layer exhibit larger saturate flat-band shift in both program and erase operation.The optimized device achieves a 7 V memory window and good reliability characteristics.

Impact of band-engineering to the performance of charge trapping memory with HfO_2 / Ta_2O_5 / HfO_2 (HTH) as tie charge trapping layer is investigated. Compared with devices with the same total HfO_2 thickness, structures with Ta_2O_5 closer to substrates show larger program / erase window, because the 2nd HfO_2 (next to blocking oxide) serving as part of the blocking oxide reduces the current tunneling out of / in the charge trapping layer during the program and erase. Moreover, trapped charge centroid is modulated and contributed more to the flat-band voltage shift.Further experiments prove that devices with a thicker 2nd HfO_2 layer exhibit larger saturate flat-band shift in both program and erase operation. The optimized device achieves a 7 V memory window and good reliability characteristics.