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射极功能逻辑(EFL)是一类新的逻辑线路形式。它基于非反相门的结构,是为大规模集成而设计的。EFL 线路的传播延迟小于同样功率的反相器门;由于在低电源电压下工作,因此降低了功耗。而且因为不用转换,可直接地实现最小化的布尔方程式,故逻辑设计也简化了。这就是说,人们可以用“与”和“或”函数,而不是用“与非”和“或非”。由于采用多发射极晶体管以及把几个多射极晶体管合并于一公共隔离区内,使得门结构的面积利用率提高了。甚至用保守的双极结型隔离工艺,可以达到较高的性能,即2～5微微焦耳。现在大多数逻辑系列都基于反相门的概
Emitter Function Logic (EFL) is a new type of logic circuit. It is based on the structure of non-inverting gates and is designed for large-scale integration. EFL line propagation delay is less than the same power inverter gate; due to low power supply voltage, thus reducing power consumption. And because without conversion, the Boolean equation can be directly minimized, so the logic design is simplified. That is to say, people can use “and” and “or” functions instead of “and” and "or not. Due to the use of multiple emitter transistors and the incorporation of several multi-emitter transistors in a common isolation area, the area utilization of the gate structure is increased. Even with the conservative bipolar junction isolation process, you can achieve higher performance, that is, 2 ~ 5 pico Joules. Most logic families are now based on inverting gates