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A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed.The frequency divider improves the quadrature phase accuracy at the output by using both input I/Q signals.Compared with conventional dividers,the circuit achieves an output I/Q phase sequence that is independent of the input I/Q phase sequence.Moreover,the third harmonic is effectively suppressed by employing a double degeneration technique. The desig n is fabricated in TSMC 0.13-μm CMOS and operated at 1.2 V.While locked at 8.5 GHz,the proposed divider measures a maximum third harmonic rejection of 45 dB and a phase noise of-124 dBc/Hz at a 10 MHz offset.The circuit achieves a locking range of 15%while consuming a total current of 4.5 mA.
A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed. The frequency divider improves the quadrature phase accuracy at the output by using both both input I / Q signals. Compared with conventional dividers, the circuit achieves an output I / Q phase sequence that The independent is the input I / Q phase sequence. Moreover, the third harmonic is effectively suppressed by employing a double degeneration technique. The design was fabricated in TSMC 0.13-μm CMOS and operated at 1.2 V. Whipped locked at 8.5 GHz, the proposed divider measures a maximum third harmonic rejection of 45 dB and a phase noise of -124 dBc / Hz at a 10 MHz offset. The circuit achieves a locking range of 15% while consuming a total current of 4.5 mA.