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本文探索了在CADENCE环境下采用Verilog－HDL工具从顶到下设计ASIC的一般方法。工作着重在单元库的建立和RTL级的逻辑综合与优化技术。从系统功能出发，进行多层次设计，Verilog－HDL设计工具可以提供强有力支持。本文通过一个设计实例介绍了Verilog－HDL设计工具的应用。
This article explores the general approach to designing ASICs from the top down using Verilog-HDL tools in CADENCE environments. Work focused on the establishment of cell libraries and RTL logic synthesis and optimization technology. From the system functions, multi-level design, Verilog-HDL design tools can provide strong support. This article describes the application of Verilog-HDL design tools through a design example.