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为满足闪存控制器中BCH解码器对速度和面积的要求,设计了一种高速小面积BCH(8528,8192,24)解码器,其关键方程电路采用简化的RiBM算法,利用二进制BCH码的特性简化关键方程电路结构和迭代轮数.使用关键方程电路的可折叠特性和逻辑资源复用,对解码器架构进行了面积优化,结果显示:与传统iBM算法相比,电路的关键路径延时减小了约50%,与RiBM算法相比,关键方程迭代轮数减少了1/2,电路资源减少了约1/3;该系统架构能够在保证吞吐率的前提下减小约70%电路面积.
In order to meet the requirement of speed and area of BCH decoder in flash memory controller, a high speed small area BCH (8528,8192,24) decoder is designed. Its key equation circuit uses a simplified RiBM algorithm and utilizes the characteristics of binary BCH code Simplify the circuit structure and the number of iterations of the key equation.Using the collapsible property of the key equation circuit and the reuse of logical resources, the area of the decoder architecture is optimized, and the results show that compared with the traditional iBM algorithm, the key path delay About 50% smaller than the RiBM algorithm, the number of iterations of key equations is reduced by 1/2, and the circuit resources are reduced by about 1/3. The system architecture can reduce the circuit area by about 70% under the premise of ensuring the throughput .