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在一些大型并行快速计算机里,往往需要将除法作为机器的一个单独的指令来完成。由于在解题过程中除法用得不多,因此目前的二进制自动计算机通常都采用经典的不恢复除法。大家知道,作一次求得 n 位商数的不恢复除法需要进行 n 次加减法及 n 次复位。在某些速度要求特别高的计算机里,当加法、乘法等运算的速度已采用了各种方法提高到一定程度以后,就有必要来考虑如何从逻辑设计上来提高除法速度的问题。
In some large parallel fast computers, it is often necessary to use division as a single instruction for the machine. As the problem-solving process is not much use of division, so the current binary automatic computer usually use the classic non-recovery division. We all know that, for once to obtain n-bit quotient of the non-recovery division method needs n times addition and subtraction and n times reset. In some computers where the speed is extremely demanding, when the speed of operations such as addition, multiplication and so on has been increased to some extent by various methods, it is necessary to consider how to improve the division speed from the logic design.