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随着前沿HVM流程节点中不断应用光刻和193nm浸没式多重图形技术,逻辑设备的关键层生产覆盖要求几乎已经达到了扫描仪硬件性能的极限。为了满足HVM生产环境极端覆盖的要求,本次研究调查了前沿技术节点的一个新集成覆盖控制构想,它将运行到运行(R2R)线性或高阶控制回路、周期逐场或每曝光校正(CPE)晶圆流程标记控制回路,以及扫描仪基线控制回路结合,应用到晶圆厂主机APC系统的一个单一集成覆盖控制路径。目标是满足晶圆厂的覆盖性能要求、降低总拥有成本,并提供自由的控制方法。本文将讨论此构想的一个详细实施案例,以及一些初步的结果。
With the continuing application of lithography and 193nm immersion multiple graphics technology to cutting-edge HVM process nodes, the critical layer production coverage requirements for logic devices have almost reached the limits of scanner hardware performance. In order to meet the extreme coverage requirements of the HVM production environment, this study investigated a new integrated overlay control concept for cutting edge technology nodes that will run into R2R linear or high-order control loops with periodic or field-per-exposure correction (CPE ) Wafer process marker control loop, and scanner baseline control loop to a single integrated overlay control path to the fab host APC system. The goal is to meet the fab’s coverage performance requirements, reduce total cost of ownership and provide free control. This article will discuss a detailed implementation of this concept, as well as some preliminary results.