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MV12片上系统采用特许半导体0.35μm、2层多晶硅4层金属(2P4M)混合信号工艺,工作电压3.3 V,包含1个MV11控制器内核和2个MV10控制器内核,采用多核异构系统架构,整个系统由高级微控制器总线架构相连。提出一种采用中断实现片上系统(SoC)多核间通信的解决方法,给出了一个挂载在高级外围总线(APB)上的具有控制多核中断功能的中断控制模块,该模块能够接收来自通用输入输出(GPIO)的输入,并产生中断信号,同时也能够接收MV10程序执行完成之后所产生的中断信号。通过中断的方式可以简化异构多核之间的通信,保证了异构多核系统MV12的高效性。所设计的中断控制器,可以作为知识产权(IP)核,挂载在任何采用APB的片上系统上。
The MV12 system-on-a-chip employs the Chartered Semiconductor 0.35μm, 2-layer polysilicon 4-layer metal (2P4M) mixed signal process with an operating voltage of 3.3 V and includes one MV11 controller core and two MV10 controller cores. The system is connected by a high-level microcontroller bus architecture. A solution to inter-chip system (SoC) inter-core communication using interrupts is proposed. An interrupt control module with multi-core interrupt control is mounted on an Advanced Peripheral Bus (APB) Output (GPIO) input, generate interrupt signals, and also receive interrupt signals generated after MV10 program execution is completed. Interrupt can simplify the communication between heterogeneous multi-core, ensuring the efficiency of heterogeneous multi-core system MV12. The designed interrupt controller can be used as an intellectual property (IP) core on any system-on-chip using APB.