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提出了一种改进的宽分频比范围可编程分频器,支持对分频数和占空比的编程设置。该结构由改进的可编程下行异步计数器和脉冲二分频器组成,采用置数自释放结构和“时间裕度借用”方法,将关键路径延时容忍度增大了一个时钟周期。提出的分频器采用0.13μm CMOS工艺进行设计与流片,版图尺寸为38.5μm×66.2μm。流片后的测试结果表明,该分频器的分频比范围为2~1 022,在分频比为m的条件下,占空比可从1/m调节至(m-1)/m。在全分频范围内,工作速度可达1.85GHz,功耗小于0.82mW。
An improved wide frequency divider range programmable divider is proposed to support the programming of frequency division and duty cycle. This architecture consists of an improved programmable downstream asynchronous counter and pulsed two-frequency divider, using a number of self-releasing architecture and a “time-based borrowing” method to increase the critical path latency tolerance by one clock cycle. The proposed divider using 0.13μm CMOS process design and flow sheet, layout size 38.5μm × 66.2μm. The test results after the flow sheet show that the frequency division ratio of the frequency divider ranges from 2 to 1 022, and the duty ratio can be adjusted from 1 / m to (m-1) / m . In the whole frequency range, working speed up to 1.85GHz, power consumption is less than 0.82mW.