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时延驱动的Ｓｔｅｉｎｅｒ树构造算法是时延驱动总体布线的基础．本文首先简介了求解最佳Ｓｔｅｉｎｅｒ树的Ｄｒｅｙｆｕｓ－Ｗａｇｎｅｒ算法．随后通过引入Ｓａｋｕｒａｉ时延模型，提出了直接基于Ｓａｋｕｒａｉ模型的提高线网时延性能的时延驱动ＤＷ算法．当集成电路工艺的特征宽度较小时，该算法求得的Ｓｔｅｉｎｅｒ树中关键点的时延值，明显小于ＩＤＷ和ＣＦＤ算法的结果．
Delay-driven Steiner tree construction algorithm is the basis of the delay-driven overall wiring. This article first introduces the Dreyfus-Wagner algorithm for solving the best Steiner tree. Then by introducing the Sakurai delay model, a delay-driven DW algorithm is proposed based on Sakurai model to improve the delay performance of the network. When the feature width of the integrated circuit is small, the delay value of the key points in the Steiner tree obtained by this algorithm is obviously smaller than the result of the IDW and CFD algorithms.