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锁相环(PLL)设计中的主要问题是满足快速信号捕获和良好同步状态两种性能的要求。本文就不同类型的相位比较器研究这一关系。结果提出一种新的相位和频率比较器。这种比较器基于升降计数器原理,并可看作是自适应捕获控制电路。对含有本文所推荐之相位比较器的锁相环分析是以牵引时间准确计算法为基础的。已证明,在不影响环路滤波性能的条件下,快速信号捕获是有可能的。文中给出了二阶2型环路捕获特性的实验结果,表明它和理论分析完全一致
The main problem in phase-locked-loop (PLL) designs is to meet both performance requirements for fast signal capture and good synchronous state. This article examines this relationship for different types of phase comparators. The result proposes a new phase and frequency comparator. This comparator is based on the up-down counter principle and can be seen as an adaptive capture control circuit. Phase-locked loop analysis with phase comparators recommended in this document is based on the accurate calculation of traction time. It has been demonstrated that fast signal acquisition is possible without affecting the performance of the loop filter. The experimental results of the second-order 2-loop catching characteristics are given, which shows that it is completely consistent with the theoretical analysis