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为了降低TFT-LCD闸驱动电路中电晶体因長期承受高的闸电压应力造成門限(Threshold)电压之劣化现象,本研究中用双下拉结构与放电路徑方式设计了一个高可靠性的TFT-LCD面板整合(On-panel)闸驱动电路。其中,交互道通的双下拉结构減少下拉电晶体的承力時間;放电路径则将输出驱动电晶体高的闸极电压及時洩放。所提结构由台积电(TSMC)0 .35μmCMOS制程技术制作之评估晶片经测试显示,门限电压的偏移量減少了近45 % ,改善效果极为显著。应用到α-Si TFT-LCD面板整合闸驱动器上,其成效当可预期。
In order to reduce the degradation of the threshold voltage caused by long-time high gate voltage stress in the TFT-LCD gate driving circuit, a high reliability TFT-LCD On-panel gate drive circuit. Wherein, the double pull-down structure of the active channel reduces the bearing time of the pull-down transistor; and the discharge path releases the high gate voltage of the output driving transistor in time. The proposed structure. TSMC 0.35μmCMOS manufacturing process of the production of the chip has been tested showed that the threshold voltage offset reduced by nearly 45%, the improvement effect is extremely significant. Applied to the α-Si TFT-LCD panel integrated gate driver, the effect can be expected.