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一、引言设计一条总线,是为了在系统中用一条公用的数据通路把几个点连接起来。一般是把几个驱动器和接收器放在导线的两端,致使数据可在每个方向流动。要求驱动器向两个方向传送信号时,常常还沿着导线把驱动器和接收器连接到总线的各点。因此,高速总线驱动器必须在一个等于线的特性阻抗一半的负载下工作。只有一个驱动器可以在任一给定的时间里传送数据。如果有多个MECL驱动器同时传输的话,那么处于高电平状态的那个输出就居于支配地位,从而引起数据丢失。
First, the introduction of a bus design, in order to use the system in a common data path to connect several points. It is common to place several drivers and receivers on both ends of the wire so that the data can flow in each direction. When the driver is required to send a signal in both directions, it is also common to connect the driver and receiver along the wire to various points of the bus. Therefore, a high-speed bus driver must operate at a load equal to half the characteristic impedance of the line. Only one drive can transfer data at any given time. If more than one MECL driver is transmitting at the same time, the output at high level dominates, causing data loss.