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本文推荐一种新的双极存贮单元,它的读/写电流与静态电流之比可达40～200;而常规存贮单元的电流比值仅为0.8～8。 在静态情况下,存贮单元的集电极阻抗是高的,在被选情况下集电极阻抗则转换至很低的数值。所推荐的器件结构采用了“挤出外延层”或“挤出基极层”,这样可以在最小的硅片面积上取得高阻值的集成电阻(或转换阻抗)。 在试验板的实验中,当静态功耗在每位50～200微瓦的范围内,这种存贮单元的存取时间小于4毫微秒,其工作周期小于15毫微秒。 采用所推荐的器件结构中的一种,制成了288位的大规模集成电路,获得了4毫微秒的选取时间和4毫微秒的写入时间。
This paper proposes a new bipolar memory cell with a read / write current to quiescent current ratio of 40 to 200 compared to 0.8 to 8 for conventional memory cells. Under static conditions, the collector resistance of the memory cell is high, and in the selected case the collector impedance translates to a very low value. The proposed device structure uses either “Extruded Epitaxial Layer” or “Extruded Base Layer” to achieve a high resistance integrated resistance (or conversion resistance) over the smallest silicon area. In experiments with the test board, when the static power consumption is in the range of 50-200 micro-watts per bit, the access time of such a memory cell is less than 4 nanoseconds and its duty cycle is less than 15 nanoseconds. Using one of the recommended device structures, a 288-bit large scale integrated circuit was fabricated with a 4 nanosecond pick-up time and a 4 nanosecond write time.