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本文讨论了适于由1位或1字节构成的MOS静态随机存储器和动态随机存储器的最佳冗余结构。64K × 1位动态随机存储器中设置了各4根备用行和列;高速16K×1位静态随机存储器中仅设置了3根备用行。这样可减少速度劣化。其中在字节构成的存储器中主要是备用行起作用。一般使用电气编程。
This article discusses the best redundancy architecture for MOS SRAMs and DRAMs consisting of 1-bit or 1-byte. 64K × 1 bit dynamic random access memory is set in the four spare rows and columns; high-speed 16K × 1 static random access memory only set three spare lines. This reduces speed degradation. Which is composed of byte memory is mainly spare line. General use of electrical programming.