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Sphere decoders are widely investigated for the implementation of multiple-input multiple-output(MIMO) detection.Among a large number of sphere decoding algorithms,the fixed-complexity sphere decoder(FSD) exhibits remarkable advantages in terms of constant throughput and high flexibility of parallel implementation.In this paper,we present a four-nodes-per-cycle parallel FSD architecture with balanced performance and hardware complexity,and several examples of VLSI implementation for different types of modulation and both real and complex signal models.Implementation aspects and architecture details are analyzed in order to present a hardware-level perspective of the FSD implementation.Therefore a variety of performance-complexity trade-offs are provided.The implementation results show that the proposed parallel FSD architecture is highly efficient and flexible,especially in the complex signal model.
Sphere decoders are widely investigated for the implementation of multiple-input multiple-output (MIMO) detection. Among a large number of sphere decoding algorithms, the fixed-complexity sphere decoder (FSD) exhibits particularly advantages in terms of constant throughput and high flexibility of parallel implementation. This paper, we present a four-nodes-per-cycle parallel FSD architecture with balanced performance and hardware complexity, and several examples of VLSI implementation for different types of modulation and both real and complex signal models. Implementation aspects and architecture details are analyzed in order to present a hardware-level perspective of the FSD implementation. Herefore a variety of performance-complexity trade-offs are provided. The implementation results show that the proposed parallel FSD architecture is highly efficient and flexible, especially in the complex signal model.