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设计了一种应用于高速时钟数据恢复电路的低压模拟相位内插器.时钟输入管和电流产生管采用隔离设计,降低了输入时钟电平变化对尾电流的影响;在输入端和输出端增加了整形电路,可有效提高相位内插器在低电压和高频工作环境下的线性度.基于TSMC 90 nm CMOS工艺进行设计,仿真结果表明:该相位内插器在1.2 V工作电压和最大90°相位差的输入时钟下,工作频率达到1.25 GHz,相位内插精度小于±10 ps,具有良好的线性度.
A low-voltage analog phase interpolator applied to high-speed clock data recovery circuit is designed. The clock input tube and the current generation tube are isolated and designed to reduce the influence of the input clock level on the tail current. The input and output terminals are increased The shaping circuit can effectively improve the linearity of the phase interpolator in low voltage and high frequency working environment.According to TSMC 90 nm CMOS technology, the simulation results show that the phase interpolator operates at 1.2 V and 90 ° phase difference input clock, the operating frequency of 1.25 GHz, the phase interpolation accuracy of less than ± 10 ps, with good linearity.