论文部分内容阅读
The conventional circuit model of a bit-stream adder based on sigma delta(∑Δ) modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit(IC) of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency.The IC is fabricated in TSMC’s 0.18-μm CMOS process.The chip area is 475×570μm~2.A fully digital∑Δsignal generator is designed with a field programmable gate array to test the chip.Experimental results show that the chip meets the function and performance demand of the design,and the chip can work at a frequency of higher than 4 GHz.The noise performance of the adder is analyzed and compared with both theory and experimental results.
The conventional circuit model of a bit-stream adder based on sigma delta (ΣΔ) modulation is improved with pipeline technology to make it work correctly at high frequencies. Integrated circuits (IC) of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency. The IC is fabricated in TSMC’s 0.18-μm CMOS process. The chip area is 475 × 570μm ~ 2.A fully digitalΣΔsignal generator is designed with a field programmable gate array to test the chip. Experimental results show that the chip meets the function and performance demand of the design, and the chip work at a frequency of higher than 4 GHz. The noise performance of the adder is analyzed and compared with both theory and experimental results.