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在制作双极逻辑集成电路中,集电区的掺杂度需要折衷。高掺杂时在发射极下做一低阻通道,低掺杂时在整个基极一集电极结上做一特定电容。实际的折衷掺杂度通常为10~(16)原子/厘米~3。英国马拉德实验室采用了比其他低,比紧挨发射极下的基极高的掺杂度。实验室制成的晶体管掺杂度为10~(16)原子/厘米~3,刚好低于发射极,而集电极体渗杂度降到10~(15)原子/厘米~3。这将集电极-基极电容降低约一半,也降低了集电极与隔离槽接触的电容。
In fabricating bipolar logic integrated circuits, the doping level of the collector region needs to be compromised. A low resistance channel is made at the emitter during high doping and a specific capacitor is made at the base-collector junction during low doping. The actual compromise doping is usually 10 ~ (16) atoms / cm ~ 3. The Mallard Laboratory in the UK uses a higher doping level than the other base, just below the emitter. The transistor made in the laboratory has a doping degree of 10-16 atoms / cm3, which is just lower than the emitter and the collector permeability decreases to 10-15 atoms / cm3. This reduces the collector-base capacitance by about half and also reduces the collector-to-spacer capacitance.