论文部分内容阅读
在工业生产中,很多控制设备利用液晶显示屏显示设备当前状态,当外部干扰使数据发送时钟错误或者数据的采集与显示速度不同,显示屏会产生画面偏移或者迟钝的现象。针对该问题,本文提出一种基于FPGA的单片SDRAM的视频缓存控制,在研究SDRAM的结构基础上,编写Verilog语言实现单片SDRAM的乒乓读写操作,利用读写时差和SDRAM的BANK切换存储,使用FIFO实现异步时钟的数据交换,提高数据吞吐量,当数据时钟受干扰时能自动刷新。本文对更功能模块进行分析,根据设计要求选择合适的FPGA和SDRAM芯片,并根据芯片设计制作PCB电路板,搭建硬件调试平台,利用一个800×480像素LCD液晶显示屏显示画面,画面稳定流畅。
In industrial production, many control devices use a liquid crystal display to display the current status of the device. When an external disturbance causes the data sending clock to be incorrect or the data collection and display speed are different, the display may have a picture offset or dullness. In order to solve this problem, this paper presents a video buffer control based on single-chip SDRAM based on FPGA. On the basis of studying the structure of SDRAM, write Verilog language to realize single-chip SDRAM read-write operation. , The use of FIFO to achieve asynchronous clock data exchange, improve data throughput, when the data clock is disturbed automatically refresh. This article analyzes more functional modules, select the appropriate FPGA and SDRAM chips according to the design requirements, and PCB circuit board based on chip design, build hardware debugging platform, the use of a 800 × 480 pixel LCD liquid crystal display screen display, the picture is stable and smooth.