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提出了一种适用于主板电压调整模块(VRM)数字控制芯片的新结构ADC——延迟环ADC的设计和实现方法.运用延时环(或称环路压控振荡器)的电压-频率转换原理实现对电压信号的模数转换,提高了线性度,减小了工艺偏差;设计差分脉冲计数式鉴频器,降低了延迟环ADC功耗.在标准0·35μm CMOS工艺环境下流片实现,测试结果表明延迟环ADC的微分线性误差和积分线性误差分别为0·92LSB和1·2LSB,最大增益误差为±3·85%,当VRM工作于稳定状态,延迟环ADC在采样频率为500kHz下工作的平均功耗为2·56mW.延迟环ADC满足VRM数字控制芯片应用要求.
A new ADC, which is suitable for the VRM digital control chip, is presented in this paper.The design and implementation of the delay ADC is described.The voltage-frequency conversion of the delay ring (or loop voltage-controlled oscillator) The principle of the analog-digital conversion of the voltage signal to improve the linearity and reduce the process deviation; differential pulse counter design differential count, reducing the delay ring ADC power consumption in the standard 0.35um CMOS process environment to achieve film, The test results show that the differential linearity error and integral linearity error of the delay loop ADC are 0.92LSB and 1.2LSB, respectively. The maximum gain error is ± 3.85%. When the VRM operates in a steady state, the delay loop ADC operates at a sampling frequency of 500kHz The average power consumption of the work is 2. 56mW. The delay ring ADC meets the application requirements of the VRM digital control chip.