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给出了寄存器传输级工艺映射 ( RTL M)算法 ,该方法支持使用高层次综合和设计再利用的现代 VL SI设计方法学 ,允许复杂的 RT级组件 ,尤其是算术逻辑单元 ( AL U)在设计中重用 .首先提出了 AL U的工艺映射问题 ,给出了源组件和目标组件以及标准组件的定义 ,在此基础上通过表格的方式给出映射规则的描述 .映射算法套用一定的映射规则用目标 AL U组件来实现源 AL U组件 .采用一种基于分支估界法的图聚集算法 ,用该算法不仅可以产生面积最优的 ,而且还可以产生延时最优的设计 .针对不同库的实验结果证明该算法对于规则结构的数据通路特别有效
A register transfer level process mapping (RTL M) algorithm is presented that supports modern VLSI design methodology using high-level synthesis and design reuse, allowing complex RT-level components, especially the ALU Design reuse.Firstly, the process mapping problem of AL U is proposed, the definitions of source components, target components and standard components are given, and then the description of mapping rules is given based on this method.The mapping algorithm applies certain mapping rules The target AL U component is used to realize the source AL U component.A graph aggregation algorithm based on branch estimation is used.It can not only produce the optimal area but also can produce the optimal delay design.Aiming at different libraries The experimental results show that the algorithm is particularly effective for the data structure of the regular structure