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今年3月29日的发布会中Intel公司发布了针对低端市场的下一代主力CPU—Coppermine-128k,包括Celeron 566和Celeron 600。它采用了0.18微米的制造工艺生产,面积减少了,这样晶体管的门电路可能被减小,才能保证在如此之小的面积上可以集成更多的晶体管,晶体管愈小,说明驱动晶体管的电流可以愈小。Coppermine在106平方毫米的芯片上集成了2800万只晶体管,几乎无法想像每个晶体管的大小,因为晶体管愈来愈小,现在采用了多层的金属技术,这种多层金属技术的核心使用绝缘材料隔绝层,以前采用的是Sio2(二氧化硅),而Coppermine为了降低电流容量,以离子植入法,植入氟化物(SiOF),这样可以提高整个芯片的传导速度。新的Celeron芯片中集成的内置二级缓存只有128kB,而Coppermine应该是有256kB的。我们当然希望二级缓存愈大愈好,因为各级缓存是CPU和主内存之间的一个重要“缓冲地带”,当运算的数据容量大于二级缓存容量时,处理器将必须直接对相对低速的内存进行读写操作,这会导
In a press conference on March 29 this year, Intel released the next-generation main CPU-Coppermine-128k for the low-end market, including the Celeron 566 and the Celeron 600. It uses a 0.18-micron manufacturing process and has a reduced area so that the gate of a transistor can be reduced to ensure that more transistors can be integrated in a small area, the smaller the transistor, indicating that the current in the drive transistor can be The smaller. Coppermine integrates 28 million transistors on a 106 mm2 chip and can barely imagine the size of each transistor as the transistor is getting smaller and now employs a multilayered metal technology that uses insulation at the heart of the multilayered metal technology Material isolation, formerly Sio2 (silicon dioxide), and Coppermine in order to reduce the current capacity, ion implantation, implantation of fluoride (SiOF), which can increase the conduction velocity of the entire chip. The new integrated Celeron chip has a built-in L2 cache of only 128kB, while Coppermine should be 256kB. Of course, we hope that the larger the level-2 cache, the better, because all levels of the cache is an important “buffer zone” between the CPU and the main memory. When the data capacity of the operation is greater than the level-2 cache capacity, the processor will have to directly address the relatively low speed Memory read and write operations, which will guide