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数字电路设计的一种新方法用来研制一种与TTL相容的新系列,即并联反馈肖特基箝位逻辑门电路。利用并联反馈放大器的实际上接近于地的输入和普通二极管偏流源的低阻抗输入实现某些逻辑操作和扇出操作,不需满幅度逻辑跳变。表决逻辑操作以及诸如与、与非、或、或非、与或、与或非等一般布尔逻辑操作都能以大约2.5nS的相同的单门延迟实现。与非门的平均功耗是17mW。叙述了串接终端传输线不需满幅度逻辑跳变。
A new approach to digital circuit design is to develop a new family of TTL compatible gates, the shunt feedback Schottky clamp logic gate. Some logic operations and fan-out operations are implemented using the virtually ground-level inputs of the shunt feedback amplifier and the low-impedance input of a normal diode bias current source, eliminating the need for full-amplitude logic transitions. Voting logic operations as well as general Boolean logic operations such as AND, NAND, OR, NOR, AND, or AND, or none, can be implemented with the same one-way delay of about 2.5 nS. The average power consumption of NAND gate is 17mW. Describes the serial termination of the transmission line does not need full-scale logic transition.