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在给定的击穿电压条件下,为了获得最小导通比电阻,采用了一个二维数字模拟程序来确定功率VDMOS结构的设计原则。为了充分考虑反型层和积累层以及VDMOS器件单元间距对击穿电压的影响,已将整个单元模型化。给出了对某一击穿电压范围内的最佳单元宽度、外延层厚度和掺杂浓度。结果表明,最佳体扩散间距随额定为～400伏的击穿电压而增大,在恒定本体宽度为15μm时导通电阻-面积乘积和击穿电压之间呈近似线性关系。
In order to obtain the minimum on-state resistance for a given breakdown voltage, a two-dimensional digital simulation program was used to determine the design principles of the power VDMOS structure. To take full account of the influence of the inversion layer and the accumulation layer and the cell spacing of the VDMOS device on the breakdown voltage, the entire cell has been modeled. The best cell width, epitaxial layer thickness and doping concentration for a breakdown voltage range are given. The results show that the optimum body-to-body spacing increases with a breakdown voltage of ~ 400 volts. An approximate linear relationship between the on-resistance-area product and the breakdown voltage is obtained for a constant body width of 15 μm.