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由中、小规模IC芯片构成的专用电路PCB微型化有重要实际意义。本文介绍基于结构的PCB逻辑再综合方法及我们开发的实验性逻辑再综合系统,系统将数字电路PCB再综合成某种工艺条件下基于标准单元实现的ASIC,其核心是利用PCB的逻辑结构并进行一系列的基于结构的冗余去除、逻辑优化及结构优化;利用标准单元匹配实现ASIC逻辑电路并进行时序调整和时间优化;经模拟正确的电路进行基于标准单元的布局布线。
The miniaturization of the special circuit PCB made up of medium and small-scale IC chips has important practical significance. This article introduces structure-based PCB logic re-synthesis method and our development of experimental logic re-synthesis system. The system integrates the digital circuit PCB into a standard-based ASIC under certain process conditions. The core of the system is to utilize the logic structure of the PCB A series of structure-based redundancy removal, logic optimization and structure optimization; the use of standard cell matching ASIC logic and timing adjustment and time optimization; by the correct simulation circuit based on the standard cell layout.