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本文根据Baugh—Wooley算法提出了实现补码乘法的二种LSI叠接逻辑阵列的新系列。整体的方法速度比较快,对大规模集成很有吸引力,但目前在尺寸上仍受到单片和封装工艺的限制。模块的方法能较好地适合于实现任意大的阵列乘法器,只是在速度上稍有降低。本文提出的带加法的乘法模块可以通过硬接线的方法,从外部编程序来实现一个二进制数的相乘,这二个数可以是补码,也可以是不带符号的格式。在构成本文所提出的模块乘法网络时,并不需外围逻辑电路,如象Wallace树或求补码器。此外,还讨论了速度分析、硬件复杂性、封装以及对该阵列乘法器的使用要求。
Based on the Baugh-Wooley algorithm, this paper presents a new series of two logic LSI logic arrays that complement the multiplication. The overall approach is faster and attractive for large-scale integration, but is still limited in size by the monolithic and packaging processes. The method of the module is better suited to implement any large array multiplier, but slightly slower in speed. The multiplication module with addition proposed in this paper can realize the multiplication of a binary number from external programming by hard-wired method, which can be two’s complement or unsigned format. In constituting the modular multiplication network proposed in this paper, does not require peripheral logic, such as Wallace tree or complement. In addition, speed analysis, hardware complexity, packaging, and usage requirements for the array multiplier are discussed.