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应用于航天工程的锁相环(PLL)电路遭受太空高能粒子轰击时会发生单粒子效应(SEE),引起电路失锁,对系统造成灾难性影响。分析了鉴频鉴相器(PFD)和分频器(DIV)模块的单粒子效应导致失锁的机理,运用改进的双互锁结构(DICE)的锁存器和冗余触发器电路分别对其进行设计加固(RHBD),基于0.35μm CMOS工艺设计了加固的锁相环电路。仿真结果表明,加固PLL可以对输入20~40 MHz的信号完成锁定并稳定输出320~640 MHz的时钟信号。在250 f C能量单粒子轰击下加固后PFD模块不会造成PLL失锁,加固DIV模块的敏感节点数目降低了80%。
Phase-locked loop (PLL) circuits used in aerospace engineering suffer from single-particle effects (SEE) when subjected to space-energetic particle bombardment, causing the circuit to lose lock and have catastrophic effects on the system. The mechanism of single-shot effect caused by PFD and DIV modules is analyzed. The latch-up and redundant flip-flop circuits with improved double interlock structure (DICE) Its design reinforcement (RHBD), based on the 0.35μm CMOS process designed to strengthen the PLL circuit. Simulation results show that the PLL can be locked to complete the input signal of 20 ~ 40 MHz and stable output 320 ~ 640 MHz clock signal. The PFD module does not lose PLL lock after reinforcement at 250 f C energy single-particle bombardment, and the number of sensitive nodes in the reinforced DIV module is reduced by 80%.